2x4 decoder with enable. It can also be found in the textbook.

2x4 decoder with enable 65-V to 5. How many NAND gates are needed to construct this line decoder? My answer of 8 was incorrect. Since a NAND gate produces the AND operation with an inverted output, it becomes more economical to generate the decoder outputs in their complement form. Enable inputs are useful for overriding the inputs and shutting off all outputs simultaneously. Jun 20, 2016 · Figure 1. Cite. Mar 8, 2022 · 2 to 4 Decoder with Enable. The truth table, logic diagram, and Full Playlist:https://www. Symbol . If the enable input "E": is 0, then all outputs are zero regardless of the input values. When the enable input is #DigitalCircuit #DLD #Microprocessor2:4 Decoder With Enable Input. #decoder #digitalelectronics #digitalsystemdesign kec 302combinational circuitdesign 2 to 4 Decoder using NOR onlydesign 2 to 4 Decoder using NAN only Exercise: Connect two 2x4 Decoders with enable inputs to build a 3x8 Decoder a) Source the 3x8Decoder outputs b) Source the data inputs of each 2x4 Decoder c) Source the enable inputs of each 2x4 Decoder D 0 D 0 A D 1 A D 1 D 2 B D 3 D 2 B D 3 D 0 D4 A D 1 C D5 D 2 B D 3 D6 D7 EN EN Aug 3, 2023 · 2x4 Decoder Usage: The outputs of A4 and A3 will serve as inputs to the 2x4 decoder to generate enable signals for the four 3x8 decoders. (Use block diagrams for your decoders) 2. Total Number of gates 4*(2 each for inverter) + 8*(8 each for AND gate). That way you can cascade them. Design a serial 2's complementer with a shift register and a flip flop. image source: wikipedia. Binary decoder has n-bit input lines and 2 power n output lines. A 2x4 decoder with an enable input can function as a demultiplexer. The 2to4 means it takes a 2 bit address and controls 4 outputs. When nE is HIGH all outputs are forced HIGH. For example, consider the 2x4 decoder with the enabled input E as shown in Figure 3. Logic gates available are inverters, OR, AND, NOR, NAND, XOR and XNOR gates. The construction of higher-order decoders Question: (5 pts) Design a 4x16 decoder with enable using five 2x4 decoders with enable. in/gate 📲 KnowledgeGate Android App: http:/ 2:4 Decoder [Detailed Explanation with logic expression and logic circuit diagram]Digital Electronic Circuit -DecoderYou can watch my all other videos here-h Q. The eight outputs of the 2x4 decoders forming the eight outputs of the 3x8 decoder. Using only 2x4 decoders with an enable, design a 3x8 decoder (without an enable input). The SN74LVC1G139 2-line to 4-line decoder is designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. When the enable input is high (1), the decoder is active and responds to the input. Nov 30, 2012 · How to build a 4x16 decoder using ONLY two 2x4 decoders? Following the steps we took in the lecture, we are supposed to build a 4x16 decoder. com/mossaied2online calculator https://www. This allows the decoder outputs to be tri-stated until the enable signal is applied. [Detailed Explaination]Please subscribe to my channel. How can I design it? I thought about it, but only 2 to 8 decoder comes out. Link. memory systems, this decoder can be used to minimize the effects of system decoding. 따라서 입력 활성화 기능이 있는 2x4 디코더(2x4 Decoder with Enable input)의 Verilog 코드를 설계하고, 이를 통해 3x8 디코더의 Verilog 코드를 설계해보자. Answer Start by drawing the block diagram for a 3x8 decoder with enable input. View. Two 2-to-4-line decoders are combined to achieve a 3-to-8-line decoder. When the enable input (E) is active (E=1 in this case), the decoder selects one of its four outputs based on the two input lines. Schematic: Logic Gate Level 2x4 Decoder with Enable List the basic logic gates you will need and their number of inputs: Alright, good. So that can hint you to use it as the Enable input for the decoder, as the enable input would be AND ed with each minterm. Specman Libraries Tools & Simulators Compile Options. 따라서 n-to-2 n decoder 은 n 개의 input들 중에. This is precisely the function of a demultiplexer, which directs a single input signal to one of several output lines. A 3x8 decoder can be implemented using one 1x2 decoder and two 2x4 decoders by using the MSB to select which 2x4 decoder is enabled Feb 4, 2025 · View Screenshot 2025-02-04 at 2. 1). Total of 72 gates were used. In a 2x4 decoder with active low enable, what would be the decoder’s output values when the inputs are 00 (that is i1=0, i0=0) and enable is 0? d0 = ? d1 = ? d2= ? d3 = ? 2)in a 2x4 decoder with active high enable, what would be the decoder’s output values when the inputs are 11 (that is i1=1, i0=1) and enable is 1? d0 = ? d1 = ? d2 (a) Implement the following Boolean function using a single 2x4 decoder with one-enable and active high outputs, and at most one logic gate. This decoder decodes the two inputs to provide four enable signals, which will activate one of the three 3x8 decoders. If you have two 2x4 decoders with an enable input, then you only need a single NOT gate to make a 3x8 decoder. This means that the effective system delay introduced by the decoder is negligible. The number of outputs is always \$2^{inputs}\$. Share. Project access type: Public Apr 17, 2021 · 이 중 DECODER 라는 것은 "detection"의 역할을 한다. Design a 5\times 32 decoder using 2\times 4 decoders with enable and one 3\times 8 decoder. Data Routing: In communication systems, a 2 to 4 decoder is used to route data to the appropriate destination based on the input combination. me/918000121313 💻 KnowledgeGate Website: https://www. com/playlist?list=PL229fzmjV9dJpNZMQx-g-NIZjUt6HLaWn Question: Circuit diagram for 2x4 decoder with active high outputs and active high enable: Figure 5: Decoder with active high enable circuit Diagram LAB TASK#1: Design and implement a 2-to-4 line decoder with active low outputs along with active low enable input E. Nov 18, 2023 · The enable input is used for making the decoder ACTIVE or INACTIVE. Construct a 5-to-32 line decoder with four 3-to-8 line decoders with enable input and one 2-to- 4 line decoder. 2 to 4 decoder: Some decoders are constructed with NAND instead of AND gates. The outputs lines 1,2,4,7 are OR-ed to give the sum, and the output lines 3,5,6,7 are OR-ed to give the carry. youtube. c) SystemVerilog module for a 2 x 4 Decoder with enable ; -k X [o ow ou,— T) Outs Knable —B 1, D, owD:D3 / 74HC139D - The 74HC139; 74HCT139 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive outputs (nY0 to nY3). It can be 2-to-4, 3-to-8 and 4-to-16 line configurations. The truth table, logic Without Enable input. is 1, then the decoder performs the normal operation. Untitled Untitled. When the device is enabled (E = low), it can be used for gating or as a data input for demultiplexing operations. Please subscribe to my channel. 5. For instance, if you did that with a 3-8 decoder, you might use only the low 4 output bits and simply not use the upper 4. Oct 2, 2020 · I want to write a behavioral level code for 2 to 4 decoder using for loop in Verilog. Here's my current solution. <p>Decoder: In Digital Electronics, discrete quantities of information are represented by binary n codes. 5-bit decoder inputs. The most significant bit is connected to the enable input of one decoder and through an inverter to the enable input of the other decoder. Mean to say, If E equals to 0 then the decoder would be considered as disabled regardless of what inputs are, If E equals to 1 then the decoder would work as per inputs. com/watch?v=qNYhbXHBvtEYou can watch all other videos here 2-to-4-Decoder Circuit. Mar 15, 2023 · شرح وافى لكيفية استنتاج عدد ال decoders المستخدمة للتصميم مع تطبيق عملى لكيفية محاكاة تصميم Question: 2x4 Decoder 20. What is the simplified SOP expression of Boolean… Answered: 2) Given the following circuit comprising a 2x4 decoder with normal outputs and one-enable. o For example, a 6-to-64 decoder can be designed with four 4-to-16 decoders and one 2-to-4 line decoder. Whether you are sharing innovative hardware designs or finding design inspiration, this is the best place for you. Feb 5, 2022 · 3:8 DECODER WITH 2:4 DECODER [Detailed Explanation and Diagram]Link for Decoder video - https://www. Now, it turns to construct the truth table for 2 to 4 decoder. Pleas May 18, 2021 · Full Playlist:https://www. Use block diagram for construction construct a 5x32 decoder with four 3x8 with enable and one 2x4 decoder. So we have 16 AND gates & two 2x4 decoders. It is therefore usually described by the number of addressing i/p lines & the number of data o/p lines. 2:4 Decoder With Enable Input. 62, but extended with an enable input: (a) create a structural HDL description of the given circuit, (b) create a testbench to test the structural description testing all possible input combinations, (c) simulate to verify correct behavior. The digital decoders are extensively used in several applications in the field of digital electronics such as decoding of data, seven segment displays, data multiplexing Mar 18, 2022 · This video explains about Decoder with enable using Active High and Active Low outputs with several examples. 0 Stars 71 Views User: Tech dude. 예를 들어 "A"라는 글자를 키보드에서 눌렀을 때, 'A를 출력해주는 회로'에 이 신호를 전달해주는 것이다. (8 pts) Use Quartus to create a structural Verilog model of a 3x8 decoder using only NAND gates and inverters. When employed with high-speed memories utilizing a fast enable circuit, the delay time of this decoder and the enable time of the memory usually are less than the typical access time of the memory. Use a block diagram for the components. [Detailed Explaination]Link for Decoder video - https://www. In the 2:4 decoder, we have 2 input lines and 4 output lines. The block diagram and truth table of 2 to 4 Decoder VHDL Code is also mentioned. Question: 1. The fig-1 depicts 2 to 4 decoder schematic symbol and following is the truth table for the same. Use block diagrams for the decoders. Follow Feb 9, 2025 · Solution For A 2x4 line decoder with enable is implemented using only NAND gates. This part is going to be the same for any 4-input function. I don’t know where to connect the other input and enable. (Use block diagrams for your decoders) 1. 2. Step 2. Given the function 𝐹 (𝐴, 𝐵, 𝐶) = 𝐴̅𝐵𝐶 + 𝐴𝐵̅𝐶 + + 𝐴𝐵𝐶̅ + 𝐴𝐵𝐶 implement using the smallest possible multiplexer. Draw this schematic in the space provided below. E input can be considered as the control input. To design the 3:8 decoder we need two 2:4 decoders. Typical decoder ICs might include two 2-4 line circuits, a 3-8 line circuit, or a 4-16 line decoder circuit Sep 2, 2017 · The 2:4 decoder will give us 4 outputs that will be connected to the 4 3:8 decoders in the enable pin for generating the output. Draw a Logic Diagram Building a 3x8 Decoder with Enable active-low, using two 2x4 decoders; also draw a truth table for the setting. Apr 25, 2023 · It can be seen that a decoder has N input lines to accept binary coded information, an enable input, E to turn on or off the decoder (optional), and 2 N unique output lines. Run Options. 3. Making 1:4 demultiplexer using 2:4 Decoder with Enable input. How many NAND gate is needed to construct this line decoder? ("8 is a wrong answer!) 2x4 decoder with enable line. com/playlist?list=PL229fzmjV9dJpNZMQx-g-NIZjUt6HLaWn Nov 5, 2021 · 2-4 decoder using NAND gates 0 Stars 3708 Views Author: Niket Bahety. Author: NIkhil Kumar. The importance is given to making c 3-8 Decoder using 2x4 decoder with enable (Gate Le D-Flip flop 栓鎖電路 Gate Level in Verilog; 2-4 Decoder with enable 具有致能的解碼器 (Gate Level) 3-to-8 Decoder 解碼器 gate level in Verilog; 用bufif1 與 bufif0 組成的 4x1 Mux 多工器 verilog 程式; 4-1 Multiplexer 多工器 (Gate Level) 2-1 Multiplexer 多工器 Apr 2, 2020 · 3-8 Decoder using 2x4 decoder with enable (Gate Le D-Flip flop 栓鎖電路 Gate Level in Verilog; 2-4 Decoder with enable 具有致能的解碼器 (Gate Level) 3-to-8 Decoder 解碼器 gate level in Verilog; 用bufif1 與 bufif0 組成的 4x1 Mux 多工器 verilog 程式; 4-1 Multiplexer 多工器 (Gate Level) 2-1 Multiplexer 多工器 construct a 5x32 decoder with four 3x8 with enable and one 2x4 decoder. Oct 9, 2020 · The concept of Decoders with Enable input for active low and active high is explained and few numerical are solved. 다음은 enable 단자를 가진 2-to-4 decoder의 verilog code입니다. Let A, B be the selection lines and EN be the input line for the demultiplexer. The name "2x4" indicates that there are two input lines and four output lines. Design a 5x32 decoder using 2x4 decoders with enable and one 3x8 decoder. 또한, 대부분의 디코더는 '입력 활성화 기능(Enable)'이 존재하며 이를 통해 비트를 늘릴수 있다. Solution for Construct a 5X32 decoder with 3X8 decoders with enable and one 2X4 decoder. 2 n 개의 output들 중 하나씩만 true가 되도록 한다. Inputs include clamp diodes. Simulate. When '4' is low U1 is enabled. I definitely know how to use a 2-to-4 decoder, and how to use a 3-to-8 decoder, but how to create a 3-to-8 decoder using only three 2-to-4 decoders is stumping me. It provides the required components, theory on how 2x4 and 3x8 decoders work, circuit diagrams, truth tables and procedures for setting up the decoders in a logic gate simulator. Since you want only one output active at a time, and because you don't have an Enable on your devices, one simple way to approach it would be to use only a subset of outputs. desmos. Project access type: Public Description: Created: Aug 31 Apr 14, 2021 · 2x4 decoder with enable line 0 Stars 77 Views Author: Prateek Goyal. Construct a 4x16 decoder using 2x4 decoders with enable. com/scientificsolving n equation in n unknowns online https://www. Jun 16, 2023 · 3. Final Answer. At this point you should have a Oct 24, 2021 · Electronics: Building a 4x16 decoder with only four 2x4 enabled decoderHelpful? Please support me on Patreon: https://www. decoder can minimize the effects of system decoding. Delete image . 26: Construct a 4-to-16-line decoder with five 2-to-4-line decoders with enable. Why? Because we need to have 8 outputs. This means that the effective system delay introduced by the decoder is Oct 8, 2017 · Pulling that line high or low depending on the decoder. Construct a 5-to-32-line decoder with four 3-to-8-line decoders with enable and a 2-to-4-line decoder. In addition, we provide ‘enable‘ to the input to ensure the decoder is functioning whenever enable is 1 and it is turned off when enable is 0. Apr 9, 2014 · The five 2:4 decoders are simply being used to construct a 4:16 decoder. Each output from this decoder represents one of the 16 possible combinations of input values. Given the Figure 6: Implementation of a 3-to-8 decoder without enable Decoder Expansion o It is possible to build larger decoders using two or more smaller ones. Dual 2-to-4 Decoder/ Demultiplexer MC74LVX139 The MC74LVX139 is an advanced high speed CMOS 2−to−4 decoder/demultiplexer fabricated with silicon gate CMOS technology. Forked from: NIkhil Kumar/2x4 decoder with enable line. 3-8 line with 2 Nov 23, 2019 · From what you have reached for the simplified SOP, you can see that "D" is present in both terms. bash shell 2 X 4 Decoder. 1. 25 PM. The objectives are to get familiar with decoders and implement a 2x4 and 3x8 decoder. Control Circuitry: The 2 to 4 decoder is often used in control circuitry to enable or disable specific functions or operations based on the input states. Set as cover image . Are you sure you want to remove this image? No Yes . The only building block I can use is a Feb 13, 2023 · In a 2x4 binary decoder, there are 2 input lines and 4 output lines. The decoder activates one of the output lines based on the binary input. A 2x4 decoder is a digital circuit that takes in two input lines, typically labeled as A and B, and an enable signal and produces four output lines based on the combinations of inputs. Q. com. 4. The enable input can be used as the data input for a 1-to-4 demultiplexer application. The enable input is an additional input line that controls whether the decoder is active or not. Each decoder features an enable input (nE). In this video blogging series, we will be explaining the Verilog coding style for various building blocks like Adder, Multiplexer, Decoder, Encoder, ALU, Flip-Flops, Counter, RAM, […] 4. 0 Stars 85 Views User: Rohan Chandra. This page of VHDL source code section covers 2 to 4 Decoder VHDL Code. Do not use any gates. A binary code of n bits is capable of representing up to 2 distinct elements of coded information. A decoder is a combinational circuit that converts binary information from n input n lines to a maximum of 2 unique output lines. It can also be found in the textbook. Importance is given to making concepts e Dec 26, 2024 · For the 2x4 decoder in Figure 2. Nov 20, 2016 · Unless I'm thinking about this wrong, with 8 AND gates and 1 NOT gate, you only need 1 2x4 decoder -- and you don't need a decoder that has an enable input. 2 to 4 decoder logic diagram: 2-to-4-line decoder with an enable input constructed with NAND gates is given below: This can be done by giving inputs a,b to both the decoders and '~c' as an enable input to the 1st decoder, and 'c' as an enable input to the 2nd decoder. The two least significant bits of the input are connected to both decoders. Construct a 16x1 multiplexer with 8x1 and 2x1 multiplexers. 25: Construct a 5-to-32-line decoder with four 3-to-8-line decoders with enable and a 2-to- 4-line decoder. patreon. Jan 15, 2025 · Solution For Study the circuits below that use a 2x4 decoder with 1 enable and active low outputs. decoder. png from EECE 2322 at Northeastern University. Result: Designed 2x4 decoder and verified by synthesizing and simulating the VERILOG code. A decoder is a combinational logic circuit that has ‘n’ input signal lines and 2 n output lines. The inputs of the resulting 3-to-8 decoder should be labeled X[2. Enable VUnit . Oct 10, 2014 · The inputs of the resulting 3-to-8 decoder should be labeled as X2 X1 X0 for the code input and E for the enable input. the outputs should be labeled Y[7. Project access type: Public Description: Created: Nov 05, 2021 Updated: Aug 27, 2023 Solution for 2) Given the following circuit comprising a 2x4 decoder with normal outputs and one-enable. This channel is created Aug 31, 2020 · 2x4 decoder with enable line 0 Stars 119 Views decoder. This is what I tried, but I always seem to get the output as 0: module decoder2x4Beh(a,e,q); input e; input [1 Apr 26, 2012 · I may be wrong, but it looks like the A and B of the decoder truth table corresponds with B and C in the top table (A being wired to the enable) In other words, the top tables A, B and C should be seen as signal names, rather than the names of pins on the decoder. 2 to 4 Decoder design using logic gates A decoder is a combinational logic circuit that has ‘n’ input signal lines and 2 n output lines. use block diagram Your solution’s ready to go! Enhanced with AI, our expert help has broken down your problem into an easy-to-learn solution you can count on. Step 1/2 To design a 5x32 line decoder, we need to use 4 3x8 decoders with enable inputs and 1 2x4 decoder. As a decoder, this circuit takes an n-bit binary number and generates an output on one of the 2n output lines. (5 pts) Design a 4x16 decoder with enable using five 2x4 decoders with enable. Schematic of 3X8 Decoder(Test Bench) with enable 2X4 Decoder is made using 4 Inverters and 8 AND gates. Use run. an Enable input which controls the overall state of the outputs –When input En is high, it functions as a –Predecoding groups: 4 + 4 for the same 8:256 decoder May 21, 2023 · 3:8 Decoder Decoders are digital circuits that convert coded inputs into multiple output lines. The 3:8 decoder has an active high Sep 6, 2024 · The [Tex]n [/Tex] selection lines of the demultiplexer are the [Tex]n [/Tex] input lines that the decoder gets and the one input line of demultiplexer is the Enable input of the Decoder. So signal B goes to pin A, signal C goes to pin B, and signal A goes to enable pin. If you must, you can use an additional gate (but you will not receive full credit). Jun 12, 2020 · In this video, you will learn how to implement and test the decoder/encoder circuit using Proteus 8. Welcome to Sarthaks eConnect: A unique platform where students can interact with teachers/experts/students to get solutions to their queries. Learning Outcome: After completion of this experiment, students are able to design Decoder circuit using Verilog VHDL. Nov 7, 2019 · This video explains how to write a synthesizable Verilog program for 2to4 Decoder using the ‘case’ statement and the importance of default statement while implementing the combinational logic. This document describes an experiment to implement a 2x4 decoder and 3x8 decoder using logic gates. . To build your schematic you will have to add some inverters to some of the device select/enable inputs. knowledgegate. The outputs should be labeled Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0. The binary number is shifted out from one side and it's 2's complement shifted into the other side of the shift register. From beginner to specialist, we can all communicate and learn together. So here taking k to be 4, k is even, so we will have \$2^k\$ so \$2^4 = 16\$ AND gates & 2 decoders each of size \$2^{k/2}\$ so \$2^2 = 4\$. You may use NAND gates having any number of inputs. This enables the use of current limiting resistors to Step 1 Refer to Lecture 7 for the logic gate level schematic of a 2x4 decoder with enable. Mar 23, 2022 · 2:4 Decoder. Aug 15, 2023 · What is an enable input on a decoder IC? Many decoders have an enable input that must be activated for the device to operate. When the enable input Y 0 connected to the enable pin of the first 2x4 decoder. Compile Options. 6. 0] for the code input and E for the enable input. Oct 7, 2014 · Using only three 2-to-4 decoders with enable and no other additional gates, implement a 3-to-8 decoder with enable. 24 0 S1 1 2 S0 EN 24 0 S1 Z X X Z G S0 EN Expre Jan 20, 2011 · (2) 소프트웨어 분야에서는 프로그래밍 언어의 경우이며, 어셈블러에서의 각 명령의 간략 기억 코드(mnemonic code)로 변환(convert)하는 역할을 하는 프로그램의 것을 디코더(decoder)라고 하는 경우가 있다. Sai Krishna Charan Dara(20171140) Characterisation of 2X4 and 3X8 Decoder March 202010/17 A 2x4 line decoder with enable is implemented using NAND gate only. 24. Binary decoder can be easily constructed using basic logic gates. com/matrix fi Nov 16, 2014 · I'd suggest working backwards from the output. 5-V V CC operation. They play a vital role in various applications where data needs to be decoded and processed. 0 . The input a[0],a[1] and a[2] is given to all the 3:8 decoders and depending on which 3:8 decoder’s enable pin is 1, corresponding output will be shown and rest all decoders will give 00000000 as the output ( 0 in Feb 6, 2016 · Binary decoder. This page of verilog sourcecode covers HDL code for 2 to 4 decoder using verilog programming language. com/watch?v=qNYhbXHBvtELink for Decoder with Enab This SN74LVC1G139 2-to-4 line decoder is designed for 1. Dec 26, 2017 · However, I don't think there is a real world decode or demux part that has two pairs of complimentary enable pins with all of the internal logic to make them work. They typically have an enable input to make it ignore the input and turn all outputs off. When '4' is high U2 is enabled. If this video benefited you in any way then give it a thumbs up and hit the SUBSCRIBE button and share with your friends who need it. VHDL Code of 2 to 4 decoder can be easily implemented with structural and behavioral modelling. codes https://github. Note that S is more significant than S0. com/playlist?list=PL229fzmjV9dJpNZMQx-g-NIZjUt6HLaWn 📝 Please message us on WhatsApp: https://wa. Example: Construct a 3-to-8 decoder using two 2-to-4 deocders with enable inputs. Students (upto class 10+2) preparing for All Government Exams, CBSE Board Exam, ICSE Board Exam, State Board Exam, JEE (Mains+Advance) and NEET can ask questions from any subject and get quick answers by subject teachers/ experts/mentors/students. May 18, 2021 · Full Playlist:https://www. 0]. Your solution’s ready to go! Our expert help has broken down your problem into an easy-to-learn solution you can count on. Use block diagrams for the components. Use the enable bit as the fifth bit. When used with high-speed memories using a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. Y 1 connected to the enable pin of the second 2x4 decoder. Answer to Solved Please draw 3x8 decoder using two 2x4 decoder with | Chegg. </p><p>(2 to 4) Decoder: The (2 to 4) decoder consists of two 2 to 4 decoder HDL Verilog Code. Design a 4x16 decoder using five 2x4 decoders with enable This is the answer but steps and the logic behind it would be great Your solution’s ready to go! Our expert help has broken down your problem into an easy-to-learn solution you can count on. com/roelvandepaarWith than Sep 24, 2022 · 많은 디코더들은 입력으로 enable 단자를 가지고 있어, enable 단자가 on일 때에만 디코더가 작동하도록 설계되어 있습니다. _____ Jun 1, 2021 · I want to design a 3 to 8 decoder with enable using three 2 to 4 decoders without enable and eight AND gates. Nov 24, 2008 · The problem asks me to make a 3-8 decoder (no enable input required), with inputs x,y,z and 8 active high outputs labelled 0-7. ciwdki fponrq fnsazroe sbln vzrmzhks jrorxhh zpo ggp sacyaw hvm mkcl uswayd hhd frg jux